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#1 |
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#2 |
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They would have to go into a non-x86 CPU design (not production, they don't make anything...they're fabless). ARM is a big market right now. But I'm not sure they'd enter the market well, it's already hyper-competitive.
Intel won't license x86 to them. And I'm not going to say anything about the stock. I don't think it'll perform too well, but I'd have sold a year ago. I'm not sure if it's worth selling now. |
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#3 |
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GPU cluster computing is awesome.
Our currently code, with just a few parts set to use GPUs would prefer to have 10 GPUs per CPU. It is possible that we could design it to use GPUs even more, only one person has tried and with only one module of code. I am not sure I would build a cluster without GPUs right now. JM |
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#4 |
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http://en.wikipedia.org/wiki/Advanced_Vector_Extensions
New features * The size of the SIMD vector registers is increased from 128-bits XMM registers to 256-bits registers called YMM0 - YMM15. Existing 128-bit instructions use the lower half of the YMM registers. Further extensions to 512 or 1024 bits are expected in the future. * Non-destructive instructions. The AVX instruction set allows all two-operand XMM instructions to be modified into non-destructive three-operand forms where the destination register is different from both source registers. For example a:=a+b is replaced by c:=a+b so that register a is unchanged after the instruction. AVX does not support non-destructive forms of instructions using general purpose registers (e.g. EAX), but such support may be added in future instruction sets. * The alignment requirement of SIMD memory operands is relaxed. Applications Suitable for floating point-intensive calculations in multimedia, scientific and financial applications. Increases parallelism and throughput in floating point SIMD calculations. Reduces register load due to the non-destructive instructions. |
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#9 |
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#11 |
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